Age: 50Y, Female, Exp:12 Y
All boards ,
All
Charni Road , Mumbai
Work History<br><br>HDL Consulting, Mumbai JUNE 2000 TO PRESENT<br><br>• Seeking ON LINE TUTION for ICSE Mathematics CLASS 8/9/10<br><br>• Developing Practical Modules for Design /Programming / Testing in HDL Languages IEEE 1076 /IEEE 1364.<br><br>TO Set up a Design Center<br>Design and Development of MegaCells / IP Cores, Modeling of Standard Cell Libraries, Standardisation of EXISTING Engineering Designs, Engineering REUSE, Library Management, Engineering Management, Design of INSTRUCTION MANUALS, PROGRAMMING Standards, STYLES, Design Methodology, Programming Methods, Development of<br>Library of Function Calls / Procedures COMMON TO ALL MegaCells as per Product Family<br><br>HDL Class / Course, Workshop - Seminar<br>Design of Training Modules, Top Bottom Designs<br>Case Study Models include<br>• Instruction Register Model<br>• Pipeline CPU<br>• Cache Memory System<br>• Abstract Data Types, FIFO, Ordered Collection<br>• MICROPROGRAM Instruction Register Model<br><br>Models are being developed in Turbo Pascal, Basic & C. Goal is to show usage of a Standard Programming Language for Modeling Digital System Components<br><br>Silicon Interfaces, Mumbai, Design Engineer SEP 1994 TO MAY 2000<br><br>Design and Testing of LANCE (~AMD7990) (Local Area Network Controller for Ethernet) in HDL IEEE 1076 Using Top Down Design Methodology for 3SOFT (UK), a Mentor Graphics Company<br>• Design of Control and Status Registers (CSR), Memory / Buffer Management Unit (DMA), Control Unit, FIFO<br>• IEEE 802.3 Standards, ETHERNET<br>• Test Plan Design and Development<br><br>Library Development for Cadence, India in HDL IEEE 1076 / IEEE 1364<br>• Test Plan Design and Development<br>• Standard Cells ALU, BINARY UP / DOWN, SHIFT Register<br><br>Visiting Instructor for Diploma in VLSI Designs, CDAC Pune<br><br>Designed and Developed a Training Program / Training Manual at Silicon Interfaces for HDL Designs. Focus on Top Bottom Design Philosophy, Test Planning, Language Constructs, Programming Methods, Programming Conventions / STYLES. (MAY 1998 TO MAY 2000)<br><br>Used INDUSTRY Standard Systems for Design / Test / Programming in HDL Languages<br><br>Attended VLSI 1997 Conference at Hyderabad & VLSI 2000 Conference at Calcutta<br><br>Undergone Training Program by CG CoreEl Systems, Pune for Programmable Logic<br>Exposure to Multi Disciplinary Fields<br><br>Marketing of TRACK (Personal Information Management Systems), Contact ( Sales Management System), Simatics - 1076 (Schematic To VHDL Design Entry System)<br><br>_______________________________________________________<br><br>Neela Asbestos, Mumbai FEB 1992 TO AUGUST 1994<br><br>Design and Development of Management Information System.<br>Modules for Accounting<br>• Bank Book, Cash Book, Journal, Debtors Ledger, Creditors Ledger, General Ledgers, Sales Commision, Sales Register, Purchase Register<br>Modules for Billing, Document Management System<br>Modules Developed in DbaseIII Plus<br>_________________________________________________________<br><br>Motorola, CA, USA, Design Engineer JULY 1991 TO SEP 1991<br><br>Design of MUX, 1.76 U Process<br>______________________________________________________<br><br>Xicor, CA, USA, Design Engineer OCT 1987 TO FEB 1991<br><br>Design of EEPROM and NOVRAM Memory Products.<br><br>X28C256 EEPROM (256 K Bit EEPROM, 1.5 U Process)<br>Design of High Speed Read Path, Recall Architecture, Row/Column Redundant Architecture, Write Control Logic, Mass / Page / Byte Mode<br><br>X20C16 NOVRAM (16 K Bit NOVRAM, 1.5 U Process)<br>Design of High Speed Read Path, Recall Architecture, Row/Column Redundant Architecture, Write Path, Design of Static RAM Memory Cell, Design of STORE Cycle to store Data from Static RAM Memory to EEPROM Memory<br>_____________________________________________________
<strong>VLSI </strong> up to Masters <br> <strong>Maths </strong> up to 10th grade-Secondary <br> <strong>Physics </strong> up to 10th grade-Secondary <br> <br><p>
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